1. Priority Info This application claims priority from Korean Patent Application Number 2003-46799, filed Jul. 10, 2003, that we incorporate here by reference.
2. Field of the Invention
The present invention relates to high-voltage generators and, more specifically, to charge pump circuits operating responsive to a mode that enables selection of a power voltage or an external high voltage.
3. Discussion of the Related Art
FIG. 1 is a block diagram of a conventional charge pump circuit. As shown in FIG. 1, the conventional charge pump circuit comprises a voltage level sensing block 20, an oscillator 30, and a charge pump block 10. The voltage level sensing block 20 senses a level of the output voltage Vout. The oscillator 30 generates pulse signals PUL, /PUL responsive to a signal DET output from the block 20. The charge pump block 10 performs a pumping operation.
The voltage level sensing block 20, as shown in FIG. 2, comprises a differential amplifier. The voltage level sensing block 20 operates responsive to a pumping enable signal enPUMP and compares output voltage Vout with reference voltage VREF. The voltage level sensing block 20 generates a level sensing signal DET.
As shown in FIG. 3, the oscillator 30 comprises one NOR gate G1 and four invertors INV1, INV2, INV3 and INV4. And the oscillator 30 responds to the level sensing signal DET to generate the complimentary pulse signals PUL, /PUL.
The charge pump block 10 comprises a charge supply part 11 and a plurality of charge pump parts 12-15. The charge supply part 11 receives an external voltage VCC and provides supply charges to a first charge pump part PSI. The charge pump parts PS1, PS2, PS3, . . . , PSn are serially connected. The charge pump parts 12-15 generate an output voltage Vout by pumping charges supplied from the charge supply part 11. An odd number of pump parts 11-15 operates responsive to the pulse signal PUL, while an even number of them operate responsive to the inverted pulse signal/PUL.
The conventional charge pump shown in FIG. 1 operates as follows.
When the pumping enable signal enPUMP is in a predetermined logic level, e.g., becomes high, the voltage level sensing block 20 senses the level of the output voltage Vout by comparing output voltage Vout to a reference voltage VREF. If the reference voltage VREF is larger than the output voltage Vout, the voltage level sensing block 20 generates the level sensing signal DET having a predetermined state, e.g., high. On the other hand, if the output voltage Vout is larger than reference voltage VREF, the voltage level sensing block 20 generates the level sensing signal DET having e.g., a low state. The oscillator 30 provides the pulse signals PUL and/PUL to the charge pump parts PS1, PS2, PS3, . . . , PSn responsive to the level sensing signal DET. That is, if the level sensing signal (DET) is enabled, all charge pump parts PS1, PS2, PS3, . . . , PSn increase the level of the output voltage Vout. If the level sensing signal (DET) is disable, all charge pump parts PS1, PS2, PS3, . . . , PSn decrease the level of the output voltage Vout.
The conventional charge pump circuit pre-charges the output voltage Vout corresponding to the external voltage VCC at each node of the charge supply part 11 and the charge pump parts 12-15. Accordingly, the time to precharge increases in the output voltage Vout. This additional time is undesired, particularly where testing integrated chips that require high voltages quickly. A need remains for an improved charge pump circuit.